1) Field
Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of patterning semiconductor or other wafers and dies.
2) Description of Related Art
In three-dimensional (3D) packaging applications, in addition to through silicon via (TSV) formation and redistribution layer (RDL) pattern formation for a silicon (Si) wafer, glass substrates have also been proposed for interposer fabrication. Accordingly, through glass via formation and RDL pattern formation approaches may be advantageous.
The use of plasma etch technology for TSV and redistribution layer pattern formation in Si wafers will need to be made more cost effective in order to gain industry acceptance. In the case of using a glass substrate as an interposer, through glass via (TGV) and redistribution layer (RDL) pattern formation is needed. There is great potential for cost savings, but no consensus has reached on suitable TGV and RDL pattern formation processes. Laser ablation has been proposed but such a process faces the same factors in its competition with plasma etch for TSV and RDL pattern formation in a Si wafer, such as heat affected zone, thermal damage, via size control, etc.